GNU Make

Martin Všetička
2011

GNU Make | Terminology

• Target is usually a file that is generated by a program.
  • An exception is PHONY TARGETS.
• Prerequisite is a file that is used as input to create the target.
• Recipe - shell commands
  • Note: Each recipe line starts with a tab character!!
• Rule explains how and when to remake certain files which are the targets of the particular rule.

Rule syntax:

target ... : prerequisites ...        myprog: prog.c lib.c
       recipe                              gcc -o myprog prog.c lib.c
       ...

GNU Make | Recipes

• The lines in the recipe are executed by invoking a new subshell for each line of the recipe, unless the .ONESHELL special target is in effect.

Example:

.PHONY test clean
test: 
    tmpDir="/tmp"  # variable in shell
    mkdir $$tmpDir/my_project_name  # does not know the 'tmpDir' variable!

clean:
    -rm -f *.o   # first '-' is processed via make 
                 # and suppresses errors of the rm command
    +echo "Done" # The line is run in a subshell despite 
                 # the make's flags '-n' (just print), '-t' (touch) and 
                 # '-q' (question) 
             

GNU Make | Makefile

• Makefile is text file. Standard makefile names are:
  GNUmakefile, makefile and Makefile.
• Makefiles contain five kinds of things:
  • explicit rules,
  • implicit rules,
  • variable definitions,
  • directives, and
  • comments (# character).

GNU Make | A Simple Makefile

 edit : main.o kbd.o command.o insert.o \
        search.o files.o
         cc -o edit main.o kbd.o command.o insert.o \
                    search.o files.o 
 main.o : main.c defs.h
         cc -c main.c
 kbd.o : kbd.c defs.h command.h
         cc -c kbd.c
 command.o : command.c defs.h command.h
         cc -c command.c
 insert.o : insert.c defs.h buffer.h
         cc -c insert.c
 search.o : search.c defs.h buffer.h
         cc -c search.c
 files.o : files.c defs.h buffer.h command.h
         cc -c files.c
 clean :
         rm edit main.o kbd.o command.o search.o files.o

GNU Make | Order of rules and default goal

• The order of rules is not significant, except for determining the default goal: the target for make to consider, if you do not otherwise specify one.
• The default goal is the target of the first rule in the first makefile.
• Run make with default goal:

  $ make

• Run make with specifying the goal (=target):

  $ make targetname

GNU Make | include directive

• The include directive tells make to suspend reading the current makefile and read one or more other makefiles before continuing.
• The directive is a line in the makefile that looks like this:
  

  include filenames...

• Example with wildcards:

  include foo *.mk

  is equivalent to:

  include foo a.mk b.mk c.mk

• Usage: When several makefiles need to use a common set of variable definitions or pattern rules.

GNU Make | include directive (2)

• Absolute path (starts with slash) - only specified file
• Relative path (does not start with slash)
  1. Current directory is searched
  2. Directories specified with -I or --include-dir.
  3. Then the following directories (if they exist) are searched, in this order:
     
     /usr/gnu/include,
     /usr/local/include,
     /usr/include.

GNU Make | Phony targets

• Sometimes you want to specify an action rather than a file as the target.
• Properties of phony targets:
  • File 'clean' would prevent the recipe from being run.
  • Better performance: implicit rules are skipped
  • Convenient command: $ make clean
• Example:

            
  .PHONY: clean  # make's rule: target '.PHONY', prerequisite 'clean'
  clean:
          rm *.o temp
            

GNU Make | Static Pattern Rules

• Syntax:
  

  targets ...: target-pattern: prereq-patterns ...
         recipe
         ...

• Each target is matched against the target-pattern to extract a part of the target name, called the stem. This stem is substituted into each of the prereq-patterns to make the prerequisite names (one from each prereq-pattern).
• Example:

  objects = foo.o bar.o
  all: $(objects)
  $(objects): %.o: %.c
         $(CC) -c $(CFLAGS) $< -o $@

GNU Make | Variables

• A variable is a name (any case-sensitive sequence of characters not containing ':', '#', '=') defined in a makefile to represent a string of text, called the variable's value.
• Variables can be used in targets, prerequisites, recipes, and other parts of the makefile.
• Variables can represent:
  • lists of file names,
  • options to pass to compilers, ...
• Example:
  

  objects = program.o foo.o utils.o # set variable's value
  program : $(objects)              # variable usage
         cc -o program $(objects)   # variable usage
  

GNU Make | Variables and their flavours (1)

1. Recursively expanded variable:
   • They are defined by lines using '='
     (or by define directive for values with newlines).
   • The value is stored verbatim and expanded whenever the value is substituted.
   • Examples:

     foo = $(bar)
     bar = $(ugh)
     ugh =                    Hi there!                    
     all:;echo $(foo)   # prints 'Hi there!' (whitespace is gone!)

     CFLAGS = $(include_dirs) -O  # It is OK because value is ... 
     include_dirs = -Ifoo -Ibar   # ... stored verbatim! (advantage)
     CFLAGS = $(CFLAGS) -O        # INFINITE LOOP! (disadvantage)

GNU Make | Variables and their flavours (2)

2. Simply expanded variables:
   • They are defined by lines using ':='.
   • The value of a simply expanded variable is scanned once and for all, expanding any references to other variables and functions, when the variable is defined.
   • Example:

     x := foo
     y := $(x) bar
     x := later
     

     is equivalent to

     y := foo bar
     x := later

GNU Make | Appending More Text to Variables

• Syntax: variable += text to append
• Example:

  objects = main.o foo.o bar.o utils.o
  objects += another.o

• Example:

  objects := main.o foo.o bar.o utils.o
  objects += another.o

• Syntax is the same for both flavours of variables!

GNU Make | substitution reference

• Syntax: $(variable:a=b)
• A substitution reference replaces every a at the end of a word with b in that value, and substitute the resulting string.
• Example:

  foo := a.o b.o c.o
  bar := $(foo:.o=.c) # variable 'bar' contains: 'a.c b.c c.c'

• Notes:
  • Syntax shortcut for the patsubst expansion function
  • Provided mainly for compatibility reasons

GNU Make | How Variables Get Their Values

• Simple assignment of an variable in a makefile.
• Variables from command line argument:

  $ make variablename=value   # make looks for '=' character

  Note: Ordinary assignments of the same variable in the makefile are ignored. You may override them though:

  override var1 = value    # recursive expanded variable
  override var2 := value   # simple expanded variable
  # To append more text to a variable defined on the command line:
  override var3 += more text

  Why is it useful?

  CFLAGS=-g                # serves as default value 
  cc -c $(CFLAGS) foo.c
  

  and in shell run: $ make CFLAGS='-g -O'.

GNU Make | How Variables Get Their Values (2)

• Automatic variables:

  lib: foo.o bar.o lose.o win.o
         ar r lib $^  # $^ contains the names of all the ...
                      # ... prerequisites, with spaces between them.

  • These variables have values computed afresh for each rule that is executed, based on the target and prerequisites of the rule.
  • There is plenty of automatic variables: $@, $<, $?, $^, etc.
• Environmental variables
  • Every environment variable that make sees when it starts up is transformed into a make variable.
  • However, an explicit assignment in the makefile, or with a command argument, overrides the environment.

GNU Make | Functions for Transforming Text

• General syntax: $(function arguments)
• Example: $(subst ee,EE,feet on the street) Returns: fEEt on the strEEt
• A few functions:
  • $(subst from,to,text)
  • $(patsubst pattern,replacement,text)
  • $(dir names...)
  • $(notdir names...)
  • $(suffix names...)
  • $(basename names...)
  • $(addsuffix suffix,names...)
  • $(wildcard pattern)

GNU Make | Common goals (1)

• There are common goals in makefiles:
  • all - Make all the top-level targets the makefile knows about.
  • clean - Delete all files that are normally created by running make.
  • install - Copy the executable file into a directory that users typically search for commands; copy any auxiliary files that the executable uses into the directories where it will look for them.
  • print - Print listings of the source files that have changed.
  • check, test - Perform self tests on the program this makefile builds.

GNU Make | Common goals (2)

• distclean, realclean, clobber - Any of these targets might be defined to delete more files than clean does. For example, this would delete configuration files or links that you would normally create as preparation for compilation, even if the makefile itself cannot create these files.
• tar - Create a tar file of the source files.
• shar - Create a shell archive (shar file) of the source files.
• dist - Create a distribution file of the source files. This might be a tar file, or a shar file, or a compressed version of one of the above, or even more than one of the above.

GNU Make | Implicit rules and variables (1)

• Implicit rules tell make how to use customary techniques so that you do not have to specify them in detail when you want to use them.
• Example: C compilation typically takes a .c file and makes a .o file. So make applies the implicit rule for C compilation when it sees this combination of file name endings.
• Example:

  foo.o: foo.c

• More realistic usage of implicit rules:

  foo : foo.o bar.o
         cc -o foo foo.o bar.o $(CFLAGS) $(LDFLAGS)

GNU Make | Implicit rules and variables (2)

• Compiling C programs
  
  • n.o is made automatically from n.c with a recipe:

    $(CC) $(CPPFLAGS) $(CFLAGS) -c

• Compiling C++ programs
  
  • n.o is made automatically from n.cc, n.cpp, or n.C with a recipe of the form:
    

    $(CXX) $(CPPFLAGS) $(CXXFLAGS) -c

GNU Make | Implicit rules and variables (3)

• $ make -p  # prints make's rules

• Suffix list: .SUFFIXES, default value:
  .out, .a, .ln, .o, .c, .cc, .C, .cpp, .p, ..., .h, ...
• Common variables used as names of programs in built-in rules:
  • CC - Program for compiling C programs; default 'cc'.
  • CXX - Program for compiling C++ programs; default 'g++'.
  • CPP - Program for running the C preprocessor, with results to standard output; default $(CC) -E.
  • and many more..

GNU Make | Implicit rules and variables (4)

• Variables whose values are additional arguments for the programs on previous slide.
• The default values for all of these is the empty string.
• C/C++ flags:
  • CFLAGS - Extra flags to give to the C compiler.
  • CXXFLAGS - Extra flags to give to the C++ compiler.
  • CPPFLAGS - Extra flags to give to the C preprocessor and programs that use it (the C and Fortran compilers).
  • and many more..

GNU Make | Generating Prerequisites Automatically (1)

• Writing rules for C/C++ programs is a tedious work. You can use cc -M to generate make's rule.
• It is recommended for automatic prerequisite generation is to have one makefile corresponding to each source file. For each source file name.c there is a makefile name.d which lists what files the object file name.o depends on. That way only the source files that have changed need to be rescanned to produce the new prerequisites.

GNU Make | Generating Prerequisites Automatically (2)

• Pattern rule to generate a file of prerequisites (i.e., a makefile) called name.d from a C source file called name.c:

  %.d: %.c
          @set -e; rm -f $@; \
          $(CC) -M $(CPPFLAGS) $< > $@.$$$$; \
          sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $@.$$$$ > $@; \
          rm -f $@.$$$$

• The purpose of the sed command is to translate:

  main.o : main.c defs.h

  into:

  main.o main.d : main.c defs.h